1. Field
The various circuit embodiments described herein relate in general to methods and apparatuses for increasing the resolution of ramp signal generators, and more particularly to methods and apparatuses of the type described that can be used in the operation of power converters.
2. Background
Ramp generation mechanisms are very useful in power converter applications. For example, they are used to implement peak current mode control (PCMC) techniques. PCMC is often used as a control technique for power converters because of its inherent voltage feed-forward and its automatic cycle-by-cycle current limiting operation. However, power converters employing PCMC schemes often suffer from stability issues and from sub-harmonic oscillations on the output. To overcome these shortcomings, slope compensation mechanisms have been employed. One slope compensation mechanism that has been employed is a ramp signal generator using a digital-to-analog (DAC) converter.
A conventional digitally controlled ramp mechanism works by programming a starting value and a decrement value for the ramp. The decrement value is used by digital subtractor logic to decrement a DAC reference value over a predetermined number of clock cycles. This decrement amount and the number of clock cycles between each decrement together define the slope of the ramp. This is illustrated in FIG. 1, to which reference is now made.
FIG. 1 is a graph of voltage verses time, depicting the operation of a typical 10-bit DAC that generates a ramp voltage output 10 in a system that uses 3.3V as reference voltage. For ease of explanation the ramp voltage output 10 is approximated by a straight line, although it should be understood that the output is subject to a number of nonlinear influences. A decrement of one DAC step corresponding to four clock cycles is assumed. In FIG. 1, for instance, four DAC step decrements 12-15 are illustrated, each corresponding to four clock cycles. The slope value is power converter dependent, i.e., is dependent on the power stage of the application.
The ramp resolution can be measured as the difference between two closest possible ramp outputs for the same slope at a certain time instant. This is shown in FIG. 2, to which reference is now additionally made. Two possible ramp signals 10 and 20 are shown. The ramp signals 10 and 20 are generated using two consecutive starting DAC output values, ‘n’ 22 and ‘n+1’ 24 as shown. Again, a decrement of one DAC step over four clock cycles is assumed. The difference between the two consecutive DAC output values ‘n’ and ‘n+1’ is equal to the minimum possible DAC value. The maximum DAC resolution dictates this minimum possible DAC output value. For this example, the minimum possible DAC output resolution and consequently the difference between two consecutive DAC output values is approximately equal to 3.3 mV, obtained as
            DAC      ⁢                          ⁢      reference      ⁢                          ⁢      voltage              2              DAC        ⁢                                  ⁢        resolution        ⁢                                  ⁢        in        ⁢                                  ⁢        bits              =                    3.3        ⁢                                  ⁢        V                    2        10              .  
Assuming the two ramp signals originating from ‘n’ and ‘n+1’ to be approximately parallel to each other, the maximum possible ramp resolution 26 is equal to 3.3 mV, which is equal to the DAC resolution. Thus, in this system, the best possible ramp resolution is limited to the maximum DAC resolution.
A box diagram of a commonly implemented PCMC system 30 using a DAC-ramp generator in a circuit having voltage and current feedback loops is shown in FIG. 3 to which reference is now additionally made. A reference voltage, Vref, is applied on line 32 to a voltage controller 34, which also receives a feedback voltage on line 36. The feedback voltage is developed from a voltage output of a power converter 38 that is to be controlled. A simple, duty-controlled buck converter power stage is considered herein; however, the principles are equally applicable to any power converter stage with peak-current mode control. The power converter stage could be, for example, duty-controlled, frequency-controlled, phase-controlled, or the like.
The voltage loop of the voltage controller 34 produces an output 40, which provides the starting voltage value for the DAC-ramp generator circuit 42. A decrement value is applied to the DAC-ramp generator circuit 42 on line 44. The output from the DAC-ramp generator circuit 42 may be in the form illustrated in FIGS. 1 and 2 above, and provides a peak reference current command on line 46 to an analog comparator and PWM (Pulse Width Modulated) generator circuit 48.
A current feedback line 50 from the output of the power converter 38 is compared with the peak reference current command on line 46, and a control signal is applied to the power converter 38 to control the output voltage thereof. The voltage output from the power converter 38 is applied on line 52 to an analog to digital converter (ADC) 54, which generates the feedback voltage on line 36 back to the voltage controller 34.
With reference additionally to FIG. 4, various waveforms produced in the operation of the circuit 30 are shown. Thus, waveform 60 represents the output of the analog comparator and PWM generator 48. Waveform 62 represents the sensed current on line 50. Waveform 64 represents the starting voltage value of the DAC-ramp generator circuit 42 for the first switching cycle. And waveform 66 represents the next possible higher starting voltage value of the DAC-ramp generator circuit 42 for the successive switching cycle.
The peak current reference 64 is driven to keep the regulated system parameter at its desired value. For the power converter system used in this example, it is assumed that the system output voltage from the power converter 38 is the controlled parameter. Thus, the outer voltage loop, including the ADC 54, drives or controls the starting value for the ramp. The decrement value on line 44 governs the slope of the compensating ramp and is usually fixed and power stage dependent. Inc resulting ramp is the peak reference command for controlling the feedback current.
Thus, in a duty-cycle controlled power stage, every time the sensed current (the current feedback on line 50 in FIG. 3) reaches its peak reference limit set by the peak reference command on line 46, the PWM waveform is reset for the remaining time in the PWM period. The PWM waveform is set again at the start of the next PWM cycle. When the sensed current 62 reaches the ramp output that is a result of the starting value of ‘n’ 64 at point 70, the PWM output 60 is reset 72 and the sensed current 62 declines 74. At the start of the next PWM cycle 76, the sensed current 62 begins to climb again until it reaches the ramp output that is a result of the next possible starting value ‘n+1’ at point 78, resetting the PWM output 80. This process is continued, as shown. It can be seen that the widths 81, 82, 83, and 84 of the PWM output pulses vary widely from pulse to pulse.
To control a power converter using PCMC, a ramp signal is either added to the sensed current or subtracted from the peak current reference. In a digital PCMC implementation of a PCMC system of the type shown in FIG. 3, the ramp resolution is limited to the resolution of the DAC used for its generation. A high ramp resolution is important for accurate regulation of the power converter output, especially to avoid unwanted output ripple in systems employing an outer control loop with an analog to digital (ADC) converter of higher resolution than the DAC. Furthermore, there is a need for this mechanism to be software programmable via a digital controller, such as a microcontroller (MCU) or digital signal processor (DSP), which imparts more intelligence to the system and provides an ability to adaptively adjust to changing conditions for optimum system performance.
For the system shown in FIG. 3, a desired output voltage level set by Vref is assumed. It is also assumed that the ADC resolution is larger than the DAC resolution for this system. This means:ΔVc1>ΔVs where,
ΔVc1=difference between output; voltage values/levels resulting from ramp signals generated by two consecutive ramp starting values, and
ΔVs=difference between two consecutive output voltage values/levels that the ADC can distinguish.
This is shown in FIG. 5, a graph of voltage vs. time, to which reference is now additionally made. As shown, there are multiple possible ADC steps or levels 85-89 between the output levels or steps 92-93 resulting from two consecutive ramp starting values, ‘n’ and ‘n+1’. This is because of the higher ADC resolution than the possible ramp resolution. For a reference voltage value Vref 95, the possible ramp signals and PWM waveforms are shown in FIG. 4.
As seen in FIG. 4, the starting value of the ramp signal changes every cycle between ‘n’ and ‘n+1’. This is because the voltage control loop calculates the starting value of the ramp signal based on ADC feedback signal that has a higher resolution than that of the controlled ramp signal. The starting value of the ramp then oscillates between two closest starting values, ‘n’ and ‘n+1’, resulting in an output closest to the desired output.
As shown in FIG. 6, to which reference is now additionally made, this might result in steady state oscillations 96 at the system output. In FIG. 6, the output voltage oscillates between output voltages 92 and 93 resulting from respective ramp starting values of ‘n’ and ‘n+1’. These oscillations are similar to those for non-PCMC controlled converters when the ADC resolution is greater than the PWM resolution.
From the above it can be seen that low resolution of the compensating ramp signal results in a reduced number of control steps, that is, a low control resolution to control the desired output. Also, if the ADC resolution is greater than the DAC resolution, it may also result in steady state oscillations on the output. This behavior is undesirable for many power converter systems. Other solutions require a higher resolution DAC that makes for an expensive solution and also makes it difficult to integrate in an MCU or DSP.
What is needed is a method, apparatus, system, and computer program product by which a higher ramp resolution can be achieved without a corresponding increase in DAC resolution that can be implemented on digital controllers, MCUs, DSPs, or the like. Also needed is a method, apparatus, system, and computer program product that can be used in conjunction with existing ramp and DAC mechanisms in digital controllers, with minimal or no additional digital logic, and which can be implemented using simple software programmable mechanisms that allow easy adaptability for optimum performance under changing system or operating conditions and for easy portability across converter platforms.